A substrate of the silicon-on-insulator (SOI) type comprises a semiconductor film, such as silicon or an alloy of silicon (e.g., a silicon-germanium alloy), situated on top of a buried insulating layer. The buried insulating layer is commonly denoted by the acronym BOX (Buried-OXide), which is itself situated on top of a carrier substrate, such as a semiconductor well.
In FDSOI technology, the semiconductor film is totally depleted. In other words, it is composed of intrinsic semiconductor material. Its thickness is generally on the order of a few nanometers. Furthermore, the buried insulating layer is itself generally very thin, on the order of ten nanometers.
In view of the limited thickness of the semiconductor film, the source and drain regions of the transistors comprise portions that are raised with respect to the semiconductor film in such a manner as to ensure a suitable electrical connection between these regions and the channel region of the transistor.
Such raised source and drain regions (commonly denoted by those skilled in the art under the acronym RSD: Raised Source and Drain) are typically obtained by epitaxy. Epitaxial processes implement either intrinsic silicon combined with an implantation of dopants, or a doped epitaxial layer in-situ with suitable protection masks in such a manner as to differentiate the source and drain regions of the NMOS transistors and of the PMOS transistors.
The epitaxial regions need to be situated as close as possible to the channel to reduce the effective gate length. The epitaxial regions also need to be situated as far as possible from the edges of the gate to reduce the lateral stray capacitances.
As a consequence, the formation of the raised source and drain regions with appropriate shapes is a critical and costly step in fabrication of the transistors. Currently, faceted raised source and drain regions are formed. In other words, the faceted raised source and drain regions have an inclined profile such that the distance between the source or drain region and the corresponding lateral flank or sides of the gate region increases between the lower part of the epitaxial region and the upper part of this epitaxial region. Furthermore, the lateral insulating regions disposed on the sides of the gate region are formed by successively deposited layers.
The combination of these multilayer lateral insulating regions and faceted epitaxies implemented for each type of transistor (N or P) leads to very high costs. Furthermore, the use of faceted epitaxies to form the raised source and drain regions poses problems because the N and P doped in-situ epitaxies have different growth mechanisms. It is therefore particularly difficult to obtain optimum shapes for each N or P type of transistor. Furthermore, depending on the type of transistor, the epitaxies and faceted source or drain regions are exposed to a final etch of the lateral insulating region. This can lead to a local thinning of the channel which degrades the electrical behavior of the transistor.